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ISL9011
Data Sheet October 13, 2005 FN9219.1
Dual LDO with Low Noise, Low IQ, and High PSRR
ISL9011 is a high performance dual LDO capable of sourcing 150mA current from channel 1 and 300mA from channel 2. The device has a low standby current and highPSRR and is stable with output capacitance of 1F to 10F with ESR of up to 200m. A reference bypass pin allows an external capacitor for adjusting a noise filter for low noise and high PSRR applications. The quiescent current is typically only 45A with both LDO's enabled and active. Separate enable pins control each individual LDO output. When both enable pins are low, the device is in shutdown, typically drawing less than 0.1A. Several combinations of voltage outputs are standard. Others are available on request. Output voltage options for each LDO range from 1.2V to 3.6V.
Features
* Integrates two high performance LDOs - VO1 - 150mA output - VO2 - 300mA output * Excellent transient response to large current steps * Excellent load regulation: * <1% voltage change across full range of load current * High PSRR: 70dB @ 1kHz * Wide input voltage capability: 2.3V - 6.5V * Extremely low quiescent current: 45A (both LDOs active) * Low dropout voltage: typically 120mV @ 150mA * Low output noise: typically 30Vrms @ 100A (1.5V) * Stable with 1-10F ceramic capacitors * Separate enable pins for each LDO * Soft-start to limit input current surge during enable
Pinout
ISL9011 10 LD 3X3 DFN TOP VIEW
* Current limit and overheat protection * 1.8% accuracy over all operating conditions * Tiny 10 Ld 3x3mm DFN package
10 VO1 9 8 7 6 VO2 NC NC GND
VIN EN1 EN2 CBYP NC
1 2 3 4 5
* -40C to +85C operating temperature range * Pin compatible with Micrel MIC2211 * Pb-free plus anneal available (RoHS compliant)
Applications
* PDAs, Cell Phones and Smart Phones * Portable Instruments, MP3 Players * Handheld Devices including Medical Handhelds
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL9011 Ordering Information
PART NUMBER (Notes 1, 2, 3) ISL9011IRVVZ ISL9011IRNNZ ISL9011IRNJZ ISL9011IRNFZ ISL9011IRNCZ ISL9011IRMNZ ISL9011IRMMZ ISL9011IRMKZ ISL9011IRMJZ ISL9011IRMGZ ISL9011IRMSZ ISL9011IRLLZ ISL9011IRLBZ ISL9011IRKNZ ISL9011IRKKZ ISL9011IRKJZ ISL9011IRKFZ ISL9011IRKCZ ISL9011IRJNZ ISL9011IRJMZ ISL9011IRJJZ ISL9011IRJRZ ISL9011IRJFZ ISL9011IRJCZ ISL9011IRJSZ ISL9011IRJBZ ISL9011IRGMZ ISL9011IRGCZ ISL9011IRRMZ ISL9011IRRKZ ISL9011IRRCZ ISL9011IRFNZ ISL9011IRFMZ ISL9011IRFJZ ISL9011IRFTZ ISL9011IRFCZ ISL9011IRDMZ ISL9011IRTJZ ISL9011IRPLZ PART MARKING DAAL DAAM DTAA DVAA DAAN DAAP DANA DBBJ DAAR DAAS DAAT DAMA DAAV DAAW DWAA DYAA DABA DAEA DAAY DALA DBBA DAKA DBCA DAJA DBDA DACA DBEA DAHA DBFA DBGA DBHA DBJA DBKA DADA DBLA DBMA DBNA DBPA DAGA VO1 VOLTAGE 3.6V 3.3V 3.3V 3.3V 3.3V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 2.9V 2.9V 2.85V 2.85V 2.85V 2.85V 2.85V 2.8V 2.8V 2.8V 2.8V 2.8V 2.8V 2.8V 2.8V 2.7V 2.7V 2.6V 2.6V 2.6V 2.5V 2.5V 2.5V 2.5V 2.5V 2.0V 1.9V 1.85V VO2 VOLTAGE 3.6V 3.3V 2.8V 2.5V 1.8V 3.3V 3.0V 2.85V 2.8V 2.7V 1.6V 2.9V 1.5V 3.3V 2.85V 2.8V 2.5V 1.8V 3.3V 3.0V 2.8V 2.6V 2.5V 1.8V 1.6V 1.5V 3.0V 1.8V 3.0V 2.85V 1.8V 3.3V 3.0V 2.8V 1.9V 1.8V 3.0V 2.8V 2.9V TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-free) 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN PKG. DWG. # L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C
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FN9219.1 October 13, 2005
ISL9011 Ordering Information (Continued)
PART NUMBER (Notes 1, 2, 3) ISL9011IRCNZ ISL9011IRCMZ ISL9011IRCLZ ISL9011IRCJZ ISL9011IRCRZ ISL9011IRCFZ ISL9011IRSNZ ISL9011IRSLZ ISL9011IRSJZ ISL9011IRBUZ ISL9011IRBLZ ISL9011IRBKZ ISL9011IRBJZ ISL9011IRBCZ NOTES: 1. Add -T to part number for tape and reel. 2. For other output voltages, contact Intersil Marketing. 3. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. Standard products are listed in Bold text. Contact Intersil Marketing on the availability and lead time of other listed devices. PART MARKING DBRA DBSA DBTA DBVA DBWA DBYA DBBB DBBC DBBD DBBE DBBF DBBG DAFA DBBH VO1 VOLTAGE 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.6V 1.6V 1.6V 1.5V 1.5V 1.5V 1.5V 1.5V VO2 VOLTAGE 3.3V 3.0V 2.9V 2.8V 2.6V 2.5V 3.3V 2.9V 2.8V 3.1V 2.9V 2.85V 2.8V 1.8V TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-free) 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN PKG. DWG. # L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C
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FN9219.1 October 13, 2005
ISL9011
Absolute Maximum Ratings
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN+0.3)V
Thermal Information
Thermal Resistance (Notes 5, 6) JA (C/W) JC (C/W) 3x3 DFN Package . . . . . . . . . . . . . . . . 50 10 Junction Temperature Range . . . . . . . . . . . . . . . . .-40C to +125C Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300C
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . . .-40C to 85C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 6. JC, "case temperature" location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40C to +85C; VIN = (VO+1.0V) to 6.5V with a minimum VIN of 2.3V; CIN = 1F; CO = 1F; CBYP = 0.01F SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER DC CHARACTERISTICS Supply Voltage Ground Current
VIN Quiescent condition: IO1 = 0A; IO2 = 0A IDD1 IDD2 One LDO active Both LDO active @25C
2.3
6.5
V
25 45 0.1 1.9 1.6 2.1 1.8
40 60 1.0 2.3 2.0 +1.8
A A A V V % %/V % % mA mA
Shutdown Current UVLO Threshold
IDDS VUV+ VUV-
Regulation Voltage Accuracy Line Regulation Load Regulation
Variation from nominal voltage output, VIN = VO+0.5 to 5.5V, TJ = -40C to 125C VIN = (VOUT+1.0V relative to highest output voltage) to 5.5V IOUT = 100A to 150mA (VO1 and VO2) IOUT = 100A to 300mA (VO2)
-1.8 -0.2 0 0.1
0.2 0.7 1.0
Maximum Output Current
IMAX
VO1: Continuous VO2: Continuous
150 300 350 475 125 300 250 200 145 110 600 200 500 400 325
Internal Current Limit Dropout Voltage (Note 8)
ILIM VDO1 VDO2 VDO3 VDO4 IO = 150mA; VO > 2.1V (VO1) IO = 300mA; VO < 2.5V (VO2) IO = 300mA; 2.5V VO 2.8V (VO2) IO = 300mA; VO > 2.8V (VO2)
mA mV mV mV mV C C
Thermal Shutdown Temperature
TSD+ TSD-
AC CHARACTERISTICS Ripple Rejection (Note 7) IO = 10mA, VIN = 2.8V(min), VO = 1.8V, CBYP = 0.1F @ 1kHz @ 10kHz @ 100kHz Output Noise Voltage (Note 7) IO = 100A, VO = 1.5V, TA = 25C, CBYP = 0.1F BW = 10Hz to 100kHz (Note 7) 70 55 40 30 dB dB dB Vrms
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FN9219.1 October 13, 2005
ISL9011
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40C to +85C; VIN = (VO+1.0V) to 6.5V with a minimum VIN of 2.3V; CIN = 1F; CO = 1F; CBYP = 0.01F (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER
DEVICE START-UP CHARACTERISTICS Device Enable TIme LDO Soft-start Ramp Rate EN1, EN2 PIN CHARACTERISTICS Input Low Voltage Input High Voltage Input Leakage Current Pin Capacitance NOTES: 7. Guaranteed by design and characterization. 8. VOx = 0.98 * VOx(NOM); Valid for VOx greater than 1.85V. VIL VIH IIL, IIH CPIN Informative 5 -0.3 1.4 0.5 VIN+0.3 0.1 V V A pF TEN TSSR Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO(nom) Slope of linear portion of LDO output voltage ramp during startup 250 30 500 60 s s/V
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FN9219.1 October 13, 2005
ISL9011 Typical Performance Curves
0.8 0.6 OUTPUT VOLTAGE, VO (%) 0.4 0.2 -40C 0.0 -0.2 -0.4 -0.6 -0.8 25C VO = 3.3V ILOAD = 0mA OUTPUT VOLTAGE CHANGE (%) 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2 6.6 -0.10 0 50 100 150 200 250 300 350 400 85C 25C -40C VIN = 3.8V VO = 3.3V
85C
INPUT VOLTAGE (V)
LOAD CURRENT - IO (mA)
FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT)
0.10 0.08 OUTPUT VOLTAGE CHANGE (%) 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 -40 VIN = 3.8V VO = 3.3V ILOAD = 0mA
FIGURE 2. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
3.4 IO = 0mA VO1 = 3.3V
3.3 OUTPUT VOLTAGE, VO (V)
3.2 IO = 150mA 3.1
3.0
2.9
2.8 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125
3.1
3.6
4.1
4.6
5.1
5.6
6.1
6.5
INPUT VOLTAGE (V)
FIGURE 3. OUTPUT VOLTAGE CHANGE vs TEMPERATURE
FIGURE 4. OUTPUT VOLTAGE vs INPUT VOLTAGE (VO1 = 3.3V)
350 300 DROPOUT VOLTAGE, VDO (mV) 250 VO2 = 2.8V 200 150 100 VO1 = 3.3V 50 0 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 400
2.9 IO = 0mA 2.8 OUTPUT VOLTAGE, VO (V) VO2 = 2.8V
2.7 IO = 150mA 2.6 IO = 300mA 2.5
2.4
2.3
2.6
3.1
3.6
4.1
4.6
5.1
5.6
6.1
6.5
INPUT VOLTAGE (V)
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (VO2 = 2.8V)
FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT
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FN9219.1 October 13, 2005
ISL9011 Typical Performance Curves
175 VO1 = 3.3V 150 DROPOUT VOLTAGE, VDO (mV) 125 85C 100 75 50 25 0 0 25 50 75 100 125 OUTPUT LOAD (mA) 150 175 200 25C -40C GROUND CURRENT (A) 50 125C 45 25C -40C
(Continued)
55
40
35 VO1 = 3.3V VO2 = 2.8V IO(BOTH CHANNELS) = 0A 25 3.0 3.5 4.0 4.58 5.0 5.5 6.0 6.5
30
INPUT VOLTAGE (V)
FIGURE 7. VO1 DROPOUT VOLTAGE vs LOAD CURRENT
200 180 160 GROUND CURRENT (A) 140 120 100 80 60 40 20 0 0 50 100 150 200 250 VIN = 3.8V VO1 = 3.3V VO2 = 2.8V 300 350 400 85C -40C 25C GROUND CURRENT (A)
FIGURE 8. GROUND CURRENT vs INPUT VOLTAGE
55
50
45
40
35 VIN = 3.8V VO = 3.3V ILOAD = 0A BOTH OUTPUTS ON 25 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125
30
LOAD CURRENT (mA)
FIGURE 9. GROUND CURRENT vs LOAD
VO1 = 3.3V VO2 = 2.8V IL1 = 150mA VIN VO1 IL2 = 300mA
FIGURE 10. GROUND CURRENT vs TEMPERATURE
VO2 (10mV/DIV) VIN = 5.0V VO1 = 3.3V VO2 = 2.8V IL1 = 150mA IL2 = 300mA CL-1, CL-2 = 1F CBYP = 0.01F
5 4 VOLTAGE (V) 3 2 1 VO2
3 2 1 0 5 0 0 100 200 300 400 500 600
VEN (V)
0
VO1 (V)
0
1
2
3
4
5 TIME (s)
6
7
8
9
10
700
800
900 1000
TIME (s)
FIGURE 11. POWER-UP/POWER-DOWN
FIGURE 12. TURN-ON/TURN-OFF RESPONSE
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FN9219.1 October 13, 2005
ISL9011 Typical Performance Curves
(Continued)
VO1 = 3.3V ILOAD = 150mA CLOAD = 1F CBYP = 0.01F 4.3V 3.6V 4.2V 3.5V VO2 = 2.8V ILOAD = 300mA CLOAD = 1F CBYP = 0.01F
10mV/DIV
10mV/DIV
400s/DIV
400s/DIV
FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT
FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT
100 90 VIN = 3.6V VO = 1.8V IO = 10mA CBYP = 0.1F CLOAD = 1F
VO (25mV/DIV)
80 70 VO = 1.8V VIN = 2.8V PSRR (dB) 60 50 40 30
300mA ILOAD 100A
20 10 100s/DIV 0 0.1 1 10 100 FREQUENCY (kHz) 1000
FIGURE 15. LOAD TRANSIENT RESPONSE
1000
FIGURE 16. PSRR vs FREQUENCY
SPECTRAL NOISE DENSITY (nV/Hz)
100
10
VIN = 3.6V VO = 1.8V ILOAD = 10mA CBYP = 0.1F CIN = 1F CLOAD = 1F
1
0.1 10
100
1K 10K FREQUENCY (Hz)
100K
1M
FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY
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FN9219.1 October 13, 2005
ISL9011 Pin Description
PIN # 1 2 3 4 PIN NAME VIN EN1 EN2 CBYP TYPE Analog I/O Low Voltage Compatible CMOS Input Low Voltage Compatible CMOS Input Analog I/O Supply Voltage / LDO Input: Connect a 1F capacitor to GND. LDO-1 Enable. LDO-2 Enable. Reference Bypass Capacitor Pin: Optionally connect capacitor of value 0.01F to 1F between this pin and GND to tune in the desired noise and PSRR performance. No Connection GND is the connection to system ground. Connect to PCB Ground plane. LDO-2 Output: Connect capacitor of value 1F to 10F to GND (1F recommended). LDO-1 Output: Connect capacitor of value 1F to 10F to GND (1F recommended). DESCRIPTION
5, 7, 8 6 9 10
NC GND VO2 VO1
NC Ground Analog I/O Analog I/O
Typical Application
ISL9011 VIN (2.3-6.5V) 1 ON 2 3 4 5 C1 C2 VIN EN1 EN2 CBYP NC VO1 VO2 NC NC GND 10 9 8 7 6 C3 C4 Vout 1 Vout 2
Enable 1 OFF ON Enable 2 OFF
C1, C3, C4: 1F X5R ceramic capacitor C2: 0.1F X5R ceramic capacitor
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FN9219.1 October 13, 2005
ISL9011 Block Diagram
VIN
IS1 1V QEN1 VO2 VREF TRIM LDO ERROR AMPLIFIER VO1 VO1
~1.0V
LDO-1 LDO-2 QEN1 QEN2
IS1 EN1 EN2
CONTROL LOGIC
UVLO
BANDGAP AND TEMPERATURE SENSOR
IS2
VOLTAGE REFERENCE GENERATOR
1.00V
GND
CBYP
Functional Description
The ISL9011 contains all circuitry required to implement two high performance LDO's. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9011 adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, smart thermal shutdown protection, staged turn-on and soft-start. Smart Thermal shutdown protects the device against overheating. Staged turn-on and soft-start minimize start-up input current surges without causing excessive device turnon time.
mode. During this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1A. When one or both of the enable pins are asserted, the device first polls the output of the UVLO detector to ensure that VIN voltage is at least about 2.1V. Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry power up. Once the references are stable, a fast-start circuit quickly charges the external reference bypass capacitor (connected to the CBYP pin) to the proper operating voltage. After the bypass capacitor has been charged, the LDO's power up. If EN1 is brought high, and EN2 is goes high before the VO1 output stablizes, the ISL9011 delays the VO2 turn-on until the VO1 output reaches its target level. This minimizes input current surge due to concurrent turn-on.
Power Control
The ISL9011 has two separate enable pins, EN1 and EN2, to individually control power to each of the LDO outputs. When both EN1 and EN2 are low, the device is in shutdown
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FN9219.1 October 13, 2005
ISL9011
If EN2 is brought high, and EN1 goes high before the VO2 output stablizes, the ISL9011 delays the VO1 turn-on until the VO2 output reaches its target level. If both EN1 and EN2 are brought high at the same time, the VO1 output has priority, and is always powered up first. During operation, whenever the VIN voltage drops below about 1.8V, the ISL9011 immediately disables both LDO outputs. When VIN rises back above 2.1V, the device reinitiates its start-up sequence and LDO operation will resume automatically.
Overheat Detection
The bandgap outputs a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about 145C, one or both of the LDO's momentarily shut down until the die cools sufficiently. In the overheat condition, only the LDO sourcing more than 50mA will be shut off. This does not affect the operation of the other LDO. If both LDOs source more than 50mA and an overheat condition occurs, both LDO outputs are disabled. Once the die temperature falls back below about 110C, the disabled LDO(s) are re-enabled and soft-start automatically takes place.
Reference Generation
The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. The filter includes the external capacitor connected to the CBYP pin. A 0.01F capacitor connected CBYP implements a 100Hz lowpass filter, and is recommended for most high performance applications. For the lowest noise application, a 0.1F or greater CBYP capacitor should be used. This filters the reference noise to below the 10Hz - 1kHz frequency band, which is crucial in many noise-sensitive applications. The bandgap generates a zero temperature coefficient (TC) voltage for the reference divider. The reference divider provides the regulation reference and other voltage references required for current generation and overtemperature detection. The current generator outputs references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination.
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9011 provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1F to 10F output capacitor that has a tolerance better than 20% and ESR less than 200m. The design is performance-optimized for a 1F capacitor. Unless limited by the application, use of an output capacitor value above 4.7F is not recommended as LDO performance improvement is minimal. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30s/V to minimize current surge. The ISL9011 provides short-circuit protection by limiting the output current to about 475mA. Each LDO uses an independently trimmed 1V reference. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory.
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FN9219.1 October 13, 2005
ISL9011 Dual Flat No-Lead Plastic Package (DFN)
2X A 0.15 C A D 2X 0.15 C B
L10.3x3C
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1
E
MIN 0.80 -
NOMINAL 0.90 0.20 REF
MAX 1.00 0.05
NOTES -
6 INDEX AREA TOP VIEW B
A3 b D D2 E
// 0.10 C 0.08 C
0.18
0.25 3.00 BSC
0.30
5, 8 -
2.23
2.38 3.00 BSC
2.48
7, 8 -
E2 e k L N
1.49
1.64 0.50 BSC
1.74
7, 8 -
A C SEATING PLANE SIDE VIEW A3
0.20 0.30
0.40 10 5
0.50
8 2 3 Rev. 0 3/05
D2 (DATUM B) 6 INDEX AREA (DATUM A) 1 2 D2/2
7
8
Nd NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k E2 E2/2
2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N 8 N-1 NX b 5 0.10 M C A B
e (Nd-1)Xe REF. BOTTOM VIEW C L
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2.
NX (b) 5
(A1) 9L
SECTION "C-C" CC
e TERMINAL TIP
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN9219.1 October 13, 2005

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